Two major methods for an image sensor (solid-state image sensor) already in practical use are the CCD method and the CMOS method. Both methods are primarily different in the structure and operation when pixel signals are read out. However, the two methods are similar in converting light intensity into electrical signals; photocarriers (photo-generated electric charges) generated in a light-receiving element within a picture cell in a given period of time (several msecs to a few secs in general) are accumulated, and then the amount of the accumulated electric charge is directly or indirectly detected. Although the CCD method, which has an advantage in enhancing sensitivity and density growth, has been dominant conventionally, the CMOS method, which has an advantage in low power consumption and single-chip integration with image processing circuits or the like in subsequent stages, is recently getting more and more prevalent.
As for such CMOS image sensors, a major conventionally known method of detecting light intensity is described with reference to FIGS. 12 and 13. FIG. 12 illustrates an example of waveforms for explaining the difference between the various signal read-out methods of conventional and general image sensors. FIG. 13 illustrates an example of voltage waveforms of a vertical signal line of a certain column.
(1) Active Pixel Sensor (APS) Method
Initially, a photodiode potential is reset to a reset potential VRST by applying a given inverse voltage at a certain point in time to a p-n junction diode (photodiode). Subsequently, when light falls on the photodiode, photocarriers are generated and an electric current flows to discharge the photodiode, resulting in the reduction of the photodiode potential. Since the discharge current at this time depends on the intensity of the incident light, the higher the intensity of the incident light is, the higher the potential reduction rate becomes. Based on this incident, as shown in FIG. 12(a), photodiode potential V1 is detected at the time when a predetermined time t1 has elapsed after the reset is finished, and the decreased amount (the discharged amount) from the reset potential VRST is obtained. The decreased amount of the potential will be a brightness signal reflecting the intensity of the incident light (see FIG. 13(a)). With this method, it is possible to increase the detection sensitivity by elongating the time t1 from when a photodiode potential is reset until the decreased amount of the potential is detected (i.e. the electric charge accumulation time), because the potential difference increases greatly when the detection is carried out even if the incident light is weak. With this configuration, the dynamic range is given by a ratio of the amplitude of the saturating signal to the total amount of the noise such as that of a readout circuit or that caused by the resetting operation. If the supply voltage decreases, the dynamic range is also reduced since the amplitude of the saturating signal decreases.
(2) Pulse Width Modulation (PWM) Method
In the case where a pixel value is read out with the PWM method within a readout period after a predetermined accumulation period, a ramp-shaped voltage change ΔV is applied to a photodiode potential in some way. Then, the time period from when the photodiode potential decreases to a predetermined reference voltage VREF until a predetermined time has elapsed after the starting point of the ramp-shaped voltage change is detected as the width of a pulse signal. Therefore, as illustrated in FIGS. 12(b) and 13(b), if the amount of the incident light during the accumulation period is large and the discharge amount is also large (i.e. in the case where the photodiode potential is relatively low at the point of time when the accumulation period is finished as shown by VPD′ in FIG. 12(b)), the pulse width additionally becomes large (e.g. t2′ in FIG. 12(b)). If the amount of the incident light during the accumulation period is weak and the discharge amount is small (i.e. in the case where the photodiode potential is relatively high at the point of time when the accumulation period is finished as shown by VPD in FIG. 12(b)), the pulse width ultimately becomes small (e.g. t2 in FIG. 12(b)). In these cases, at or after the point of time when the predetermined time has elapsed after the starting point of the ramp-shaped voltage change, the subsequent reset is performed as described earlier. With this method, the dynamic range is given by a ratio of the readout period per one picture cell by the PWM method to the jitter of a readout circuit. This can be rewritten by a ratio of the amplitude of the saturating signal of a photodiode to the equivalent input noise of the readout circuit, and the dynamic range can be expanded by the gain of the amplifier of a readout circuit. Therefore, this method is resistant to the reduction of a supply voltage compared to the APS method.
Recently, the CMOS image sensors are widely coming into use, e.g. in an imaging device for a camera-equipped mobile phone. In the image sensors used for such purpose, using less power as well as having a high number of picture cells are both very important. One effective method to lower the power consumption is to reduce the supply voltage. However, in general, when the supply voltage is reduced, the noise factor is not reduced while the maximum amplitude is reduced in the photoelectric conversion element in an image sensor. Therefore, the S/N ratio and the dynamic range are reduced.
As described earlier, the signal readout by the PWM method is effective in expanding the dynamic range compared to the APS method. However, in a conventionally known signal readout circuit using a source follower amplifier, it is inevitable that the dynamic range is reduced when the supply voltage is reduced. To address this problem, Non-Patent Document 1 and Patent Document 2 suggest image sensors with the aim of lowering the power consumption while maintaining the dynamic range. FIG. 14 is a configuration diagram of a suggested picture cell in an image sensor, and FIG. 15 is a timing chart showing the readout operation by the image sensor in FIG. 14.
The anode terminal of the photodiode 81 which generates the signal electric charge corresponding to the intensity of incident light is grounded. A capacitor 82 is connected between the cathode terminal and the ramp voltage signal line 86. The input terminal of the amplifier 83 is connected to the connection point of the cathode terminal of the photodiode 81 and the capacitor 82. The output terminal of the amplifier 83 is connected to the vertical signal line 89 via the MOS transistor 85 for output selection. A MOS transistor 84 for resetting is connected between the input terminal and the output terminal of the amplifier 83. The gate terminal of the MOS transistor 84 is connected to the reset signal line 87, and the gate terminal of the MOS transistor 85 is connected to the row selection signal line 88.
The signal readout operation carried out with this picture cell is hereinafter described. First, the MOS transistor 84 is turned on by the reset signal RST supplied to the reset signal line 87, and the potential of the cathode terminal of the photodiode 81 (photodiode potential), VPD, is set to the reset potential VRST (see FIGS. 15(c) and (d)). After the reset, a predetermined voltage is applied to the ramp voltage signal line 86, and then the photodiode potential VPD is raised to VRST+ΔV via the capacitor 82. Then, when light is allowed to fall on the photodiode 81, the voltage VPD gradually decreases by the photocurrent generated in the photodiode 81 as shown by the dotted line in FIG. 15(d). When a predetermined accumulation period is finished, the voltage VPD is reduced by ΔVSIG from the starting point of the accumulation period. That is, the photodiode potential VPD as of then is VRST+ΔV−ΔVSIG.
After that, the ramp voltage VRAMP which is applied to a terminal of the capacitor 82 is decreased from a predetermined voltage at a constant rate (see FIG. 15(a)). Then the photodiode potential VPD is also decreased in proportion to the ramp voltage VRAMP via the capacitor 82. Specifically, if the capacitance of the capacitor 82 is denoted by Cramp, the junction capacitance of the photodiode 81 which is connected in series with the capacitance Cramp is denoted by Cpd, and the voltage change of the ramp voltage VRAMP is denoted by ΔVramp, the voltage change ΔVpd of the photodiode potential VPD will be {Cramp/(Cramp+Cpd)}×ΔVramp. When the photodiode potential VPD crosses the threshold voltage Vth, the output is inverted and a binary signal having a pulse width according to the amount of incident light is provided (see FIG. 15(e)).
A circuit having such a configuration can be operated with a supply voltage of approximately 1[V] and the low power consumption is therefore achieved. In addition, since the gain of the amplifier is large, the equivalent input noise can be significantly reduced compared to the conventional configuration using a source follower amplifier in a readout circuit. Therefore, the high dynamic range is also achieved. Meanwhile, such an image sensor as described in the aforementioned Non-Patent Document 2 will hereinafter be called a low-voltage PWM image sensor in order to distinguish it from conventional PWM image sensors.
However, the low-voltage PWM image sensor with the conventional circuit configuration as described earlier requires a capacitor 82, which is charged by a ramp voltage, within every picture cell. In a semiconductor chip, a capacitor is an element occupying a far larger space than a transistor or other elements. Inevitably, the size of a picture cell becomes significantly large. According to an estimate by the inventors of the present invention, the size of a picture cell of such a configuration in which a picture cell includes a capacitor as described earlier is approximately four times larger than that of what is called 3Tr-type APS circuit in which one picture cell includes three MOS transistors. Therefore increasing the number of picture cells is difficult. And, to keep the same number of picture cells, the cost might be increased since the area of a semiconductor chip becomes large.
In the low-voltage PWM image sensor described in the aforementioned Non-Patent Document 1, there are two possible configurations as for an amplifier 83; one is to use one source-grounded MOS transistor, and the other is to use an inverter amplifier of a CMOS configuration in which a PMOS transistor and an NMOS transistor are incorporated. The former configuration has an advantage in the reduction of the size of a picture cell over the latter configuration because the number of transistors in a picture cell is one less. However, when the photodiode potential VPD is higher than the threshold voltage Vth of the source-grounded MOS transistor, a constant bias current flows into the transistor. In the PWM method, the key point is the timing of the changing point when the output of the amplifier 83 is inverted. In the aforementioned circuit, a bias current constantly flows while the source-grounded MOS transistor is in an on-state. Since the power consumption regarding this condition does not directly contribute to the acquisition of the required information, it can be regarded as wasted power consumption. That is, the former configuration has a disadvantage in reducing the power consumption.
On the other hand, in the case where the latter configuration, i.e. an inverter amplifier of a CMOS configuration, is used, an electric current flows only in a transient state in which the output varies, and a bias current does not flow in a static state in which the output is fixed. Therefore, it has an advantage in the power consumption. At the same time, it has a disadvantage in the reduction of the size of a picture cell since it requires two transistors as an amplifier 83. In addition, in an inverter amplifier of a CMOS configuration, a through current flows from the power supply side to the ground side when an output change occurs, while no constant bias current flows as described earlier. Therefore, under the condition that the time period when the gate-source voltage is around the threshold voltage Vth is long, e.g. in the case where the slew rate of the ramp voltage is low or in the case where the width of the transition range of the CMOS inverter amplifier is wide, there is a possibility that the power consumption by the through current may increase to a significant level. Hence, if the power consumption by a through current can be reduced, it is possible to further achieve lower power consumption more than ever before.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. H10-269345
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 2005-198149
[Non-Patent Document 1] M. Shouho, K. Hashiguchi, K. Kagawa and J. Ohta, A Low-Voltage Pulse-Width-Modulation Image Sensor. 2005 CCD & AIS, Jun. 9, 2005